Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
PLDs are used extensively in digital systems. In some systems, PLDs are configured to receive and/or transmit high-speed a digital data stream from and to other digital devices in the system along a data channel (“channel”). An ideal incoming digital data stream would have a series of square-wave-type pulses with vertical leading and trailing edges and flat ideal. However, incoming digital data streams are not perfect. Deviation from ideality can be caused by frequency-dependent attenuation of the channel over which the data is transmitted. For example, if the channel, such as a wire trace on a printed circuit board or transmission line, presents more attenuation at higher frequencies than at lower frequencies, phase distortion of the incoming digital data stream can occur.
Inter-symbol interference (“ISI”) causes bits in a data stream to become less ideal. Each bit of incoming data is “stretched” by its adjacent bits and other bits in the data stream. The resultant incoming digital data stream has pulses with sloped leading and trailing edges and rounded corners. For example, the first bit adds a small amount of voltage to the second bit to produce a summed waveform that is unlike either the first or second bit.
At the end of a long serial data communication, such as occur in systems with serializer/de-serializer (“SERDES”) receivers, the incoming waveform might not look like the waveform that was sent from the data transmitting device. SERDES receivers are used in PLDs, such as FPGAs. One way to compensate for the changes in the incoming waveform is to apply decision-feedback equalization (“DFE”). DFE applies a selected correction signal (e.g. voltage or current) to an input bit at a summing node that compensates for the frequency-dependent attenuation of the channel carrying the data to the receiver. In some systems, DFE is essentially the inverse function of the channel attenuation as a function of frequency.
DFE techniques use sampled data from the incoming digital data stream and feeds the sampled data back into the data stream based on the frequency response of the data channel. Linear devices, such as linear gain amplifiers, provide a selected amount of feedback. In other words, the feedback is provided as an analog signal, not as a digital (rail-to-rail) signal.
However, typical architectures for clocking the data in DFE circuits introduce a large load on the high-speed clock, or add delay to the data feedback path. The high-speed clock is typically about 5 GHz or more, and refers to the clock used in the DFE circuit, not the incoming data rate (e.g. 10 GHz), which is often twice the rate of the high-speed clock (e.g. 5 GHz). It is desirable to provide DFE to incoming digital data streams that put a smaller load on the high-speed clock and/or consume less power to operate and/or have less delay in the data feedback path. Less delay in the data feedback path allows the correction signal to be summed with the incoming data sooner, resulting in more accurate equalization or higher speed operation.